View AX88615_5135791.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asix electronics corporation first released date : apr/02/1999 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw ax88 615 p 5-port 10/100base ethernet switch 5-port 10/100base ethernet switch controller document no.: ax615-13 / v1.3 / aug. 11 ? 99 features support 5 10/100 mbps ethernet ports with rmii/mii interface provide s packet switching functions between 5 10/100 mbps, auto-negotiated ports ideal for soho switches and its application build in 5-ports 10/100mbps switch engine with following features low cost ssram interface to reduce system cost one or two 64k*32bit ssram to buffer packets 4/8 k mac address look up table is supported address mapping of look up table can be linear or use hash algorithm auto learning and filtering aging the look up table is supported optionally aging time can be 1 min to 640 mins 7 steps three forwarding modes are supported : store- a n d -forward, fragment-free and auto forward which is based on network quality flow-control is supported optionally 802.3x flow control is supported when running in full-duplex mode back-pressure base flow control is supported when running in half-duplex mode ext. buffer memory auto testing routing and learning at wire speed (148800 packets/sec at 100mbps) led display buffer utilization (%) for whole system and external ssram test. power on led diagnosis. all the led display will follow the ? on-off-on-off-normal ? operation procedure during/after power on reset 6 0 mhz operation, 3.3volt, 208-pin pqfp product description the AX88615 is a 5-ports 10/100 mbps ethernet switch with mii phy or rmii phy. it is design for low cost dumb switch application , e.g. soho ethernet switch, with low cost 64k*32 ssram buffer memory . key applications soho ethernet switch ip router system block diagram always contact asix for possible updates before starting a design. this data sheet contain s new products information. asix electronics reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. AX88615 switch controller 1 or 2 64k*32 ssram 1 quad rmii /mii phy rmii/mii phy for down-link or server 5 port 10/100mb soho switch
asix electronics corporation 2 confidential AX88615p 5-port 10/100mb switch controller preliminary contents 1.0 AX88615 overview ................................ ................................ ................................ ................................ ....... 4 1.1 g eneral d escription ................................ ................................ ................................ ................................ ...... 4 1.2 AX88615 b lock d iagram : ................................ ................................ ................................ .............................. 4 1.3 p in c onnection d iagram ................................ ................................ ................................ ............................... 5 2.0 pin description ................................ ................................ ................................ ................................ ........... 6 2.1 mii/rmii interface for switch ports ................................ ................................ ................................ ............ 6 2.1.1 switch port 0 ................................ ................................ ................................ ................................ .............. 6 2.1.2 switch port 1 ................................ ................................ ................................ ................................ .............. 7 2.1.3 switch port 2 ................................ ................................ ................................ ................................ .............. 7 2.1.4 switch port 3 ................................ ................................ ................................ ................................ .............. 8 2.1.5 switch port 4 ................................ ................................ ................................ ................................ .............. 8 2.2 led d isplay ................................ ................................ ................................ ................................ .................... 9 2.3 b uffer memory pins group ................................ ................................ ................................ ............................. 9 2.4 m iscellaneous ................................ ................................ ................................ ................................ .............. 10 2.5 p ower on configuration setup signals cross reference table ................................ ................................ 11 3.0 functional description ................................ ................................ ................................ ..................... 13 3.1 b asic o peration ................................ ................................ ................................ ................................ ............ 13 3.2 p acket f iltering and f orwarding p rocess ................................ ................................ ................................ 13 3.3 mac a ddress l earning and a ging p rocess ................................ ................................ .............................. 13 3.4 f low c ontrol p rocess ................................ ................................ ................................ ................................ 13 4.0 internal registers ................................ ................................ ................................ ................................ 15 5.0 electrical specification and timing ................................ ................................ .......................... 16 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 16 5.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 16 5.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 16 5.4 ac specifications ................................ ................................ ................................ ................................ ......... 17 5.4.1 lclk ................................ ................................ ................................ ................................ ....................... 17 5.4.2 reset timing ................................ ................................ ................................ ................................ ............ 17 5.4.3 rmii interface timing tx & rx ................................ ................................ ................................ ................ 18 5.4.4 mii interface timing tx & rx ................................ ................................ ................................ .................. 19 5.4.5 ssram read cycle timing ................................ ................................ ................................ ...................... 20 5.4.6 ssram write cycletiming ................................ ................................ ................................ ....................... 21 5.4.7 led display ................................ ................................ ................................ ................................ ......... 22 5.4.8 led display after reset ................................ ................................ ................................ .......................... 22 6.0 package information ................................ ................................ ................................ ........................... 23 appendix a: system applications ................................ ................................ ................................ .......... 24 a.1 AX88615 as 5- port standalone soho switch ................................ ................................ ........................... 24 a.2 AX88615 for ip router application ................................ ................................ ................................ ........... 24 a.3 AX88615 as backend of dual speed repeaters ................................ ................................ ........................... 25 appendix b: design note ................................ ................................ ................................ ............................. 26 b.1 u sing s tation m anagement (sta) c onnection ................................ ................................ ........................ 26 b.2 u sing mii i/f connects to mac ................................ ................................ ................................ .................. 26
asix electronics corporation 3 confidential AX88615p 5-port 10/100mb switch controller preliminary figures f ig - 1 AX88615 b lock d iagram ................................ ................................ ................................ ............................. 4 f ig - 2 p in c onnection d iagram ................................ ................................ ................................ .............................. 5 f ig - 3 a pplication for led display ................................ ................................ ................................ ..................... 14
asix electronics corporation 4 confidential AX88615p 5-port 10/100mb switch controller preliminary 1.0 AX88615 overview 1.1 general description the AX88615 is a 5-ports 10/100 mbps ethernet switch with mii phy or rmii phy. a low cost fast ethernet switch can be implemented by using the AX88615 and low cost 64kx32 ssram . data received from the mac interface is stored in the external memory. all ports support multiple mac addresses. the switch provides a look-up table for 8k mac addresses with two 64kx32 ssrams. the AX88615 provides three frame forwarding mode: store-and- forward mode, safe cut-through (fragment free) mode and dynamic-select-mode (auto) . the dynamic-select-mode means the switch selects optimizes mode for forwarding packages automatically according to network quality. during transmission, the data is obtained from the buffer memory and routed to the destination port. for half-duplex operation, the mac control will back off and retransmit in accordance to the ieee802.3 csma/cd if collision occurs. the AX88615 provides two flow control methods. for half-duplex operation, an optional jamming based flow control is available to avoid loss of data. this is also well known as back pressure. in the full-duplex mode, AX88615 utilizes ieee802.3x as the flow control mechanism. 1.2 AX88615 block diagram: fig - 1 AX88615 block diagram p0 10/100 mac p1 10/100 mac p2 10/100 mac p3 10/100 mac p4 10/100 mac high speed switch fabric routing /learning controller buffer manager buffer memory interface led interface mii / rmii phy mii / rmii phy mii / rmii phy mii / rmii phy mii / rmii phy 64k*32 ssram
asix electronics corporation 5 confidential AX88615p 5-port 10/100mb switch controller preliminary 1.3 pin connection diagram fig - 2 pin connection diagram 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 17 18 19 23 24 22 20 21 48 49 50 51 52 25 29 30 28 31 26 27 32 33 34 35 36 37 38 39 40 41 42 43 47 46 44 45 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 145 146 147 150 148 149 153 151 152 154 156 155 133 134 135 138 136 137 141 139 140 142 144 143 121 122 132 109 110 111 114 112 113 117 115 116 118 120 119 124 123 125 126 127 128 129 131 130 208 207 206 205 204 203 202 201 200 199 197 198 196 195 194 193 192 191 190 188 189 187 186 185 184 183 182 181 179 180 178 177 176 175 174 173 172 170 171 169 168 167 166 165 164 163 161 162 160 159 158 157 53 AX88615 vdd ref_clk lclk /rst /test vdd vss led_ck vss led<1> led<0> vss vdd vss nc nc vss vdd vss vss vdd vss bma6 bma7 bmd16 bmd20 bmd18 bmd21 bmd17 bmd22 bmd23 bmd19 vss vdd vss bma12 vss bma11 bma14 bma15 bma10 bma16 bma13 bmd7 bmd3 bmd5 bmd2 bmd6 bmd1 bmd0 bmd4 bmd15 bmd11 bmd13 bmd10 bmd14 bmd9 bmd8 bmd12 bma9 bma8 /bmoe /bmwe bmclk vss vdd mdio mdc bma5 bma1 bma4 bma3 bma2 bmd24 bmd28 bmd27 bmd31 bmd26 bmd25 bmd29 bmd30 vss srxd4[3] sduplex4 srxd4[1] stxd4[1] scol4 stxd4[0] srxd4[0] stxclk4 srxdv4 scrs4 stxd4[2] srxd4[2] stxen4 srxclk4 stxd4[3] srxd2[3] sduplex2 srxd2[1] stxd2[1] scol2 stxd2[0] srxd2[0] stxclk2 srxdv2 scrs2 stxd2[2] srxd2[2] stxen2 srxclk2 stxd2[3] srxd3[3] sduplex3 srxd3[1] stxd3[1] scol3 stxd3[0] srxd3[0] stxclk3 srxdv3 scrs3 stxd3[2] srxd3[2] stxen3 srxclk3 stxd3[3] nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc db_sel[7] nc nc nc db_sel[6] db_sel[5] db_sel[4] db_out[7] db_sel[3] db_sel[2] db_sel[1] db_sel[0] db_out[6] db_out[5] db_out[4] db_out[3] db_out[2] db_out[1] db_out[0] nc nc srxclk1 srxd1[2] scrs1 srxdv1 srxd1[0] srxd1[1] srxd1[3] stxd1[0] stxd1[1] stxd1[3] stxen1 stxd1[2] stxclk1 scol_sp1 sduplex1 stxd0[1] stxen0 stxclk0 stxd0[0] stxd0[3] stxd0[2] sduplex0 scol_sp0 srxdv0 scrs0 srxd0[0] srxclk0 srxd0[1] srxd0[2] srxd0[3] bma0 speed2 speed3 speed4 vss vdd vss nc nc nc nc nc nc nc nc
asix electronics corporation 6 confidential AX88615p 5-port 10/100mb switch controller preliminary 2.0 pin description 2.0 pin description the following terms describe the AX88615 pinout: all pin names with the ? / ? suffix are asserted low. i = input o = output i/o = input /output 2.1 mii/rmii interface for switch ports 2.1.1 switch port 0 signal name type pin no. description stxen0 o 87 transmit enable : a ctive high. this output indicates that the packet is being transmitted .if mii mode, txen0 is synchronous to stxclk0 . if rmii mode, txen0 is synchronous to ref_clk. stxd0[3:0] o 91,90,89,88 transmit data : stxd0[3:0] is synchronous to the rising edge of stxclk0 in mii mode . for each stxclk period in which stxen is asserted, txd[3:0] are accepted for transmission by the phy. if rmii mode, stxd0[1:0 ] is synchronous to ref_clk. txd0[1:0] shall be ? 00 ? to indicate idle when tx_en is disserted. value that is not ? 00 ? is reserved for out-of-band signaling and shall be ignored by phy. when tx_en is asserted, txd[1:0] are accepted for transmission by phy stxclk0 i 93 transmit clock : provides the timing reference for the stxen0 , stxd0 signals in mii mode. stxclk0 frequency is one fourth of the data rate (25 mhz for 100mbps, 2.5 mhz for 10mbps). sduplex0 i 94 duplex select : duplex0 is not standard mii/rmii signal. this input is connected to phy directly to obtain the current data rate of port0. scol_sp0 i 97 collision detect : active high. indicates a collision has been detected on wire in mii mode. this input is not synchronous to any clock and ignored in full-duplex mode if rmii mode, the signal is a speed indicator. active for 10mbps speed is selected depending on power on configuration. scrs0 or scrs_dv0 i 96 carrier sense : a ctive high. indicates that either the transmit or receive medium is non-idle in mii mode. scrs0 is not synchronous to any clock. when rmii mode, the input is crs_dv (carrier sense/receive data valid ) that is asserted asynchronously on detection of carrier by the phy when receive medium is non-idle. loss of carrier shall result in the desertion of crs_dv synchronous to the cycle of ref_clk, which presents the first di-bit of a nibble on to rxd0[1:0]. srxdv0 i 98 receive data valid : active high. indicates that valid data is present on the srxd0 lines. synchronous to srxclk0 . srxclk0 i 104 receive clock : provides the timing reference for the srxdv0 , srxd0 signals in mii mode. stxclk0 frequency is one fourth of the data rate (25 mhz for 100mbps, 2.5 mhz for 10mbps). srxd0[3:0] i 114,113, 111,110 receive data : s ynchronously to the rising edge of rxclk in mii mode . if rmii mode, srxd0[1:0] is synchronous to ref_clk . srxd0[1:0] shall be ? 00 ? to indicate idle when crs_dv is disserted. value that is not ? 00 ? is reserved for out-of-band signaling shall be ignored by mac upon assertion of crs_dv, phy shall ensure that rxd[1:0] = ? 00 ? until proper receive decoding takes place
asix electronics corporation 7 confidential AX88615p 5-port 10/100mb switch controller preliminary 2.1.2 switch port 1 signal name type pin no. description stxen1 o 60 transmit enable : please references section 2.1.1 switch port0 description. stxd1[3:0] o 64,63,62,61 transmit data : please references section 2.1.1 switch port0 description. stxclk1 i 65 transmit clock : please references section 2.1.1 switch port0 description. sduplex1 i 66 duplex select : please references section 2.1.1 switch port0 description. scol_sp1 i 76 collision detect : please references section 2.1.1 switch port0 description. scrs1 or scrs_dv1 i 75 carrier sense : please references section 2.1.1 switch port0 description. srxdv1 i 77 receive data valid : please references section 2.1.1 switch port0 description. srxclk1 i 78 receive clock : please references section 2.1.1 switch port0 description. srxd1[3:0] i 82,81,80,79 receive data : please references section 2.1.1 switch port0 description. 2.1.3 switch port 2 signal name type pin no. description stxen 2 o 165 transmit enable : please references section 2.1.1 switch port0 description. stxd 2 [3:0] o 18 7, 186, 168 , 167 transmit data : please references section 2.1.1 switch port0 description. stxclk 2 i 196 transmit clock : please references section 2.1.1 switch port0 description. sduplex 2 i 184 duplex select : please references section 2.1.1 switch port0 description. scol 2 i 202 collision detect : please references section 2.1.1 switch port0 description. scrs 2 or scrs_dv2 i 161 carrier sense : please references section 2.1.1 switch port0 description. srxdv 2 i 181 receive data valid : please references section 2.1.1 switch port0 description. srxclk 2 i 169 receive clock : please references section 2.1.1 switch port0 description. srxd 2 [3:0] i 18 3, 182, 163 , 162 receive data : please references section 2.1.1 switch port0 description. speed2 i 160 speed indicator : identify data rate of port 2
asix electronics corporation 8 confidential AX88615p 5-port 10/100mb switch controller preliminary 2.1. 4 switch port 3 signal name type pin no. description stxen 3 o 5 transmit enable : please references section 2.1.1 switch port0 description. stxd 3 [3:0] o 15,14,7, 6 transmit data : please references section 2.1.1 switch port0 description. stxclk 3 i 33 transmit clock : please references section 2.1.1 switch port0 description. sduplex 3 i 13 duplex select : please references section 2.1.1 switch port0 description. scol 3 i 34 collision detect : please references section 2.1.1 switch port0 description. scrs 3 or scrs_dv3 i 2 carrier sense : please references section 2.1.1 switch port0 description. srxdv 3 i 10 receive data valid : please references section 2.1.1 switch port0 description. srxclk 3 i 9 receive clock : please references section 2.1.1 switch port0 description. srxd 3 [3:0] i 12,11,4, 3 receive data : please references section 2.1.1 switch port0 description. speed3 i 1 speed indicator : identify data rate of port 3 2.1.5 switch port 4 signal name type pin no. description stxen 4 o 45 transmit enable : please references section 2.1.1 switch port0 description. stxd 4 [3:0] o 55,54,47, 46 transmit data : please references section 2.1.1 switch port0 description. stxclk 4 i 36 transmit clock : please references section 2.1.1 switch port0 description. sduplex 4 i 53 duplex select : please references section 2.1.1 switch port0 description. scol 4 i 37 collision detect : please references section 2.1.1 switch port0 description. scrs 4 or scrs_dv4 i 4 2 carrier sense : please references section 2.1.1 switch port0 description. srxdv 4 i 50 receive data valid : please references section 2.1.1 switch port0 description. srxclk 4 i 49 receive clock : please references section 2.1.1 switch port0 description. srxd 4 [3:0] i 52,51,44, 43 receive data : please references section 2.1.1 switch port0 description. speed4 i 41 speed indicator : identify data rate of port 4
asix electronics corporation 9 confidential AX88615p 5-port 10/100mb switch controller preliminary 2. 2 led display signal name type pin no. description led[1 :0 ] o 85, 84 ssram fail / buffer memory utilization led : v as utilization of buffer memory the buffer utilization of switch uses the following definition: 1: led off 0: led on for detail , see the led timing specification . v ssram fail led[0] : this signal also indicates sram chip 0 fail ( continue active low ) during the interval of sequence shift data. led[1] : this signal also indicates sram chip 1 fail ( continue active low ) during the interval of sequence shift data. led_ck o 86 led clock : the signal is a discontinue clock for led signals serial shift out. the clock period width is 40 0 ns and last 32 cycle with every 5 2.4 ms repeated. 2.3 buffer memory pins group signal name type pin no. description bma[16:0] o 197 ? 201 16,17 170,166 143,142 23-18 ssram a ddress bus bmd[31:24] bmd[23:16] bmd[15:8] bmd[7:0] i/o 24, 26-32 133-138 140, 141 171-173 175-179 180, 188-194 ssram d ata bus /bmwe o 158 ssram w rite strobe /bmoe o 159 ssram r ead strobe bmclk o 72 s sram clock utilization (%) uti0 uti1 uti2 uti3 uti4 uti5 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 20 0 0 1 1 1 1 40 0 0 0 1 1 1 60 0 0 0 0 1 1 80 0 0 0 0 0 1 95 0 0 0 0 0 0
asix electronics corporation 10 confidential AX88615p 5-port 10/100mb switch controller preliminary 2.4 miscellaneous signal name type pin no. description lclk i 70 local clock : 66mhz. used for system operation synchronous. /rst i 59 reset : active low the chip is reset when this signal is asserted low. ref_clk i 68 reference clock : the input is a continue clock at 50mhz for timing reference with rmii interface. /test i/pu 58 test pin : active low the pin is just for test mode setting purpose only. must be pull high when normal operation. mdio i/o 57 station management data in/out : t o read phy auto negotiation remote capability register to get current speed and duplex status. (see appendix also) mdc o 56 station management data clock out : for mdio reference clock. db_sel[7:0] i/pu 132-129, 119-116 debug mode selection : enable debug selection when /test pin = 0 db_out[7:0] o 148-145, 124,123, 121,120 debug mode monitor output : nc o 38,39,40, 56,57,73, 74,95,99, 100,102, 105-109, 125,126, 128, 150-156, 203-207 nc : keep no connection vdd i 25, 48, 69, 92, 122, 144, 164, 195, power : +3.3v +/-5% vss i 8, 35, 67, 71, 83, 101, 112,115, 127, 139, 149, 157, 174,185, 208 power: 0v
asix electronics corporation 11 confidential AX88615p 5-port 10/100mb switch controller preliminary 2.5 power on configuration setup signals cross reference table signal name share with description /hash_en bma[16] hash algorithm enable : 0 : enable look-up table addressing use hashing algorithm. 1 : disable look-up table addressing use linear addressing aging_s[2:0] bma[15:13] aging timer selection : aging_s2 aging_s1 aging_s0 aging time (min) 1 1 1 no aging (disable) 1 1 0 5 1 0 1 10 1 0 0 20 0 1 1 40 0 1 0 160 0 0 1 640 0 0 0 1 rxfc_en bma[12] pause identification enable : 0 : disable 802.3x receives flow control function in full duplex. 1 : enable 802.3x receives flow control function in full duplex. mii_s1 b ma[11] mii enable for p ort 1 , 2, 3, 4 : 0 : switch port 1 , 2, 3, 4 ? rmii ? mode is selected 1 : switch port 1 , 2, 3, 4 ? mii ? mode is selected mii_s0 b ma[10] mii enable for p ort 0 : 0 : switch port 0 ? rmii ? mode is selected 1 : switch port 0 ? mii ? mode is selected /part_en bma[9] tx partition enable : 0 : enable partition function of transition. 1 : disable partition function of transition. ram_s bma[5] ram size selection : external packet buffer ram size select ram_s ram size 1 64k * 32 ssram 0 128k * 32 ssram netqlty_s bma[4] network quality selection: auto forwarding mode is based on packet error percentage to select store -and-f orward or fragment free mode. netqlty_s error packet ratio 1 20% 0 40% fwtyp_s1 fwtyp_s0 bma[3] bma[2] forward type selection : fwtyp _s1 fwtyp _s0 forward mode 1 1 store & forward 1 0 store & forward 0 1 fragment free 0 0 auto hibndy_s1 hibndy_s0 bma[1] bma[0] threshold selection for flow control : flow control will be active when buffer memory is below the threshold: hibndy_s1 hibndy_s0 buffers left 1 1 64 packets 1 0 32 packets 0 1 16 packets 0 0 96 packets / flowctl _en4 stxen0 p4 flow control enable : enable flow control function of switch port 4, 802.3x for full duplex, back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. / flowctl _en3 stxd0[3] p3 flow control enable : enable flow control functions of switch port 3,
asix electronics corporation 12 confidential AX88615p 5-port 10/100mb switch controller preliminary 802.3x for full duplex, back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. / flowctl _en2 stxd0[2] p2 flow control enable : enable flow control functions of switch port 2, 802.3x for full duplex, back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. / flowctl _en1 stxd0[1] p1 flow control enable : enable flow control function s of switch port 1, 802.3x for full duplex, back pres s ure for half duplex. 0 : enable flow control function. 1 : disable flow control function. /flowctl_en0 stxd0[0] p0 flow control enable : enable flow control function s of switch port 0, 802.3x for full duplex, back pre s sure for half duplex. 0 : enable flow control function. 1 : disable flow control function. speed_s1 stxd1[2] speed setting for port 1, 2, 3, 4 : in rmii mode, speed ? scol_sp1 ? pin function selection 0 : p ort 1 , 2, 3, 4 rmii mode, scol_sp1 pin is low for 10m,high for 100m 1 : p ort 1 , 2, 3, 4 rmii mode, scol_sp1 pin is low for 100m,high for 10m speed_s0 stxd1[1] speed setting for port 0 : in rmii mode, speed ? scol_sp0 ? pin function selection 0 : p ort 0 rmii mode, scol_sp0 pin is low for 10m,high for 100m 1 : p ort 0 rmii mode, scol_sp0 pin is low for 100m,high for 10m fdpxhi_s1 stxd1[0] duplex setting for port 1, 2, 3, 4 : p ort 1 , 2, 3, 4 ? sduplex1 ? pin function select 0 : sduplex1 pin is low for half duplex,high for full duplex 1 : sduplex1 pin is low for full duplex,high for half duplex fdpxhi_s0 stxen1 duplex setting for port 0 : p ort 0 ? sduplex0 ? pin function selection 0 : sduplex0 pin is low for half duplex,high for full duplex 1 : sduplex0 pin is low for full duplex,high for half duplex /rdphy_en s txd 4 [0] mdio read phy register 05h information 0 : enable 1 : disable pktlenopt s txd3[0] maximun packet length selection 0 : 1522 byte 1 : 1518 byte all of the above signals are pull-up for default values.
asix electronics corporation 13 confidential AX88615p 5-port 10/100mb switch controller preliminary 3.0 functional description 3. 1 basic operation in general, the basic operation of the switch is very simple. the switch receives incoming packets from one of its ports , searches in the look-up table for the destination mac address and then forwards the packet to the destination ports, if appropriate. if the destination mac address is not found in the look-up table, the switch treats the incoming packet as a broadcast packet and forwards it to all ports except itself. basically the switch automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. the device is updated the table with the source mac address if the source mac address does not exist the table. 3. 2 packet filtering and forwarding process during the receiving process, the switch will monitor the length of the received packet. legal ethernet packets should have a length of no less 64 bytes and nor more than 1528 bytes. the switch discards any packet with illegal length . after a packet is received, its source mac address and destination mac address are received. the source mac address is used to update the look-up table and the destination mac address is used to determine the destination port of the packet. once a mac address has been learned, and the packet is buffered, it must be forwarded, that is, the packet forwarding mechanism for the switch is handled automatically based on the destination mac address. under the following conditions, received packets are filtered: the switch will check all received packets for errors, e.g., fcs error, runt packet, long packet, etc. any packet handing to its own source port will be filtered. that is, its destination port is its source port. the incoming packet will be discarded if the switch ? s buffer memory is full. the switch supports t hree forwarding modes: store- a n d -forward, fragment-free and auto . store- a n d -forward mode: an entry packet is received, checked and stored in the buffer memory before it is forwarded. that is, each forwarded packet is correct. fragment-free mode: it is a simple improvement on cut-through method. the switch will forward a packet whose packet length is more than 64 bytes. all runt packet s will be filtered in fragment-free mode. auto mode: in auto mode, the switch select dynamically its optimized forwarding mode based on the current network quality of each port. 3. 3 mac address learning and aging process t he switch can learn up to 8k unique mac addresses with a hashing algorithm . addresses are stored in the look-up table located in external ssram, then each packet updates the table . the table lookup engine provides the switching information required routing the data packets. the address table is set up through auto address learning dynamically. after the switch receives a packet , the source mac address and destination mac address are received. the source address retrieved from the received packet is automatically stored in a sa buffer. the switch will check for error and perform a sa search. the switch will update the look-up table with the source mac address if there is no error. the look-up table is cleared on power-on, or hardware reset. when the aging option is enabled, the dynamically learned sa will be cleared if it is not refreshed in less than configured time (2 or 5 min). 3. 4 flow control process the switch can operate at two different modes: half-duplex and full-duplex. each port can be configured to have flow control enabled or not. the switch supports 802.3x for full-duplex operation and uses back pressure for half-duplex. in full-duplex mode, the switch will receive and transmit the packet in accordance to 802.3x. the transmission channel and the receiving channel operate independently. if the occupancy of the buffer memory is above the flowcontrolactive
asix electronics corporation 14 confidential AX88615p 5-port 10/100mb switch controller preliminary threshold, the mac of port will send out a pause frame with maximum delay. the switch will send out a pause frame with zero delay after below flowcontrolactive threshold. for the receiving channel, the switch will not transmit the next packet whenever received a pause frame with non-zero delay. the switch will resume packet transmission either after the pause timer expired or a pause frames with zero delay received. in half-duplex mode, the switch will receive and transmit the packet in accordance to 802.3 csma/cd. if the occupancy of the buffer memory is above the flowcontrolactive threshold, the mac of port will send out jam pattern . 3.5 led display interface AX88615 provides led status indication for memory test and packet buffer utilization (%). all led[2:0] perform active low. led[2:0] status driver wave-form as follows : led_ck led[0] led[0] continue led[1] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d10 d15 led[1] continue sw uti0 sw uti1 sw uti2 sw uti3 sw uti4 sw uti5 d16 d19 d20 d21 d22 d18 d23 d17 ( this portation no clock presented ) chip 0 memory test fail and/or 100m collision chip 1 memory test fail and/or 10m collision n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a it must use external shift register to decode data on led[1]. the application shows as follows: 74ls164(#1) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d led[1] led_ck 74ls164(#2) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d sw uti0 sw uti5 sw uti4 sw uti3 sw uti2 sw uti1 fig - 3 application for led display
asix electronics corporation 15 confidential AX88615p 5-port 10/100mb switch controller preliminary 4.0 internal registers (this page keep blank)
asix electronics corporation 16 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.3 +4.0 v input voltage vin -0.3 vdd+0.5 v output voltage vout -0.3 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +3.0 +3.6 v 5.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.3 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min tpy max units power consumption pc tbd ma note : 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
asix electronics corporation 17 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4 ac specifications 5.4.1 lclk lclk tr tf tlow bmclk tod symbol description min typ. max units t cyc cycle time 16.6 ns t high clk high time 6.64 8.3 9.96 ns t low clk low time 6.64 8.3 9.96 ns t r/ t f clk slew rate 1 - 4 ns tod lclk to bmclk out delay 2 ns 5.4.2 reset timing ref_clk /rst symbol description min typ. max units trst reset pulse width 10 - - ref_clk tcyc thigh
asix electronics corporation 18 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4.3 rmii interface timing tx & rx t0 t1 ref_clk t2 t3 tx_en txd crs_dv t2 t3 rxd symbol description min typ. max units t0 ref_clk clock cycle time 19.998 20 20.002 ns t1 ref_clk clock high time 7 10 13 ns t2 crs_dv, rxd, txen and txd data setup to ref_clk rising edge 4 ns t3 crs_dv, rxd, txen and txd data hold from ref_clk rising edge 2 ns
asix electronics corporation 19 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4.4 mii interface timing tx & rx t0 t1 txclk t2 t2 tx_en t3 t3 txd symbol description min typ. max units t0 txclk cycle time 39.996 40 40.004 ns t1 txclk high time 14 20 26 ns t2 tx_en delay from txclk high 7.440 21.760 ns t3 txd delay from txclk high 3.410 13.320 ns t4 t5 rx_clk crs t 6 rxdv t 7 rxd rxer symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t 6 crs to rxdv delay requirement 40 160 ns t 7 rxd or rxdv setup to rx_clk rise time 10 - ns
asix electronics corporation 20 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4.5 s sram read cycle timing bmclk bma[16:0] /bmwr / bmoe bmd[7:0] symbol description min max units t1 clock cycle time 15 - ns t2 address bus setup time 2.5 - ns t3 address bus hold time 0.5 - ns t4 clock to output invalid 2 - ns t5 clock to output valid - 6 ns t5 t4 d1 t3 a1 t2 t1
asix electronics corporation 21 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4.6 s sram write cycletiming bmclk bma[16:0] /bmwr / bmoe bmd[7:0] symbol description min max units t1 clock cycle time 15 - ns t2 address bus setup time 2.5 - ns t3 address bus hold time 0.5 - ns t 4 write data setup time 2.5 - ns t7 write data hold time 0.5 - ns t5 t4 a1 t3 t2 t1 d1
asix electronics corporation 22 confidential AX88615p 5-port 10/100mb switch controller preliminary 5.4.7 led display led_ck -------- - ~ ~ ------- d0 d1 d2 .............. d22 d23 d0 d1 d2 led_ck led[1:0] symbol description min typ. max units t1 led_ck clock cycle time 400 ns t2 clock to output valid 206.5 ns t3 clock to output invalid 200 ns t4 continuous 32 led_ck cycle time 52.4 ms 5.4.8 led display after reset /reset t1 t2 t2 t2 t3 led[ 1 :0] symbol description min typ. max units t1 repeater reset time 1000 ns t2 led blink time after reset 838.4 ms t3 led dark time before normal display 419.2 ms t4 t1 d1 d0 d15 ? . d3 d2 d0 t3 t2 t1
asix electronics corporation 23 confidential AX88615p 5-port 10/100mb switch controller preliminary 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.05 0.25 0.5 a2 3.17 3.32 3.47 b 0.10 0.20 0.30 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e 0.50 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.45 0.60 0.75 l1 1.30 q 0 10
asix electronics corporation 24 confidential AX88615p 5-port 10/100mb switch controller preliminary appendix a: system applications a.1 AX88615 as 5-port standalone soho switch a.2 AX88615 for ip router application AX88615 switch controller quad rmii phy single phy AX88615 switch controller quad rmii phy ax88195 or ax88196 local cpu bus mac controller
asix electronics corporation 25 confidential AX88615p 5-port 10/100mb switch controller preliminary a.3 AX88615 as backend of dual speed repeaters buffer 10mbps and 100mbps horizontal cascade 10mbps and 100mbps vertical cascade upto 4 stacks ax88873 #0 repeater controller 2 quad rmii phy 2 quad rmii phy ax88873 #1 repeater controller buffer 10mbps and 100mbps horizontal ax88873 #0 repeater controller 2 quad rmii phy 2 quad rmii phy ax88873 #1 repeater controller AX88615 5-port switch controller quad phy single phy 10m link 100m
asix electronics corporation 26 confidential AX88615p 5-port 10/100mb switch controller preliminary appendix b: design note b.1 using station management (sta) connection there are two methods to get per port speed and duplex information in a x 88615 . one way is by hardware pins such as speed0, sduplex0, speed1, sduplex1 . AX88615 also provides 2 pins (mdc and mdio , sta ? station management connection ) to read phy auto negotiation remote capability register to get current speed and duplex status. when use sta function, the connected phy address settings must be fixed as follows: port 0 port 1 port 2 port 3 port 4 0fh 10h 11h 12h 13h the corresponding option setting /rdphy_en = 0 b.2 using mii i/f connects to mac using mii interface to connect to mac type device application for AX88615 is illustrated bellow. 3.3v 10k * 2 10k gnd AX88615 / switch ax88195 / mac note : 1. the mac needs to run at fullduplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embbeded mac can also refer to this example sduplex0 scol_sp0 stxen0 stxclk0 stxd0[3:0] scrs0 srxdv0 srxclk0 srxd0[3:0] col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock bma[10] stxen1

▲Up To Search▲

Price & Availability of AX88615

	To Download AX88615 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .